1. Statement of the Technical Field
The present invention relates to cache memory management and more particularly to cache tuning.
2. Description of the Related Art
Memory cache technologies have formed an integral part of computer engineering and computer science for well over two decades. Initially embodied as part of the underlying hardware architecture of a data processing system, data caches and program instruction caches store often-accessed data and program instructions in fast memory for subsequent retrieval in lieu of retrieving the same data and instructions from slower memory stores. Consequently, substantial performance advantages have been obtained through the routine incorporation of cache technologies in computer main board designs.
Notably, the inherent principles of the data cache have been applied far beyond the realm of the computer main board. In this regard, caching technologies have been implemented across numerous computing systems ranging from soft database management systems, to hard drive controlling technologies. Data caching technologies have become particularly important in the context of content delivery systems in which often-requested content can be cached for frequent distribution to requesting computing clients.
In the prototypical content delivery system, content can be delivered from an origin server to a community of content consuming clients. Content typically can be delivered according to a request-response paradigm in which the content consuming clients initiate a request for content to which one or more origin servers can respond with the requested content. Generally, one or more content caches can be disposed in the intermediate communications path between the content consuming clients and content servers in order to enhance the responsiveness of the servers to any single client request and to reduce the processing burden placed upon the origin server.
Notably, it has been well-documented that the successful use of a cache can depend upon the size of the cache. Specifically, it is well-known that cache performance—namely the hit ratio of a cache—can vary non-linearly with the size of the cache. To account for this non-linear relationship, cache administrators generally perform manual cache tuning in order to optimize the performance of a cache by varying the size of the cache. The manual variance of the cache can be determined based upon the contemporarily experienced performance of the cache and the corresponding size of the cache when measuring the contemporary performance.
It will be recognized by the skilled artisan that manually tuning a cache can be difficult and inexact. Consequently, several automated cache tuning methods have been proposed. For example, in U.S. Pat. No. 5,732,240, the size of a cache can be dynamically modified and the resulting improvement in the hit rate can be measured. The cache size can be repeatedly changed until the resulting improvement falls negative. That is, when the “peak” improvement has been detected, the cache size can be considered optimal. Nevertheless, to reach the optimal cache size setting, one must “test” multiple cache size settings in a linear fashion and the process of reaching the optimal setting can be slow and inefficient.
To avoid the linear searching methodology of the '240 patent, several automatic cache tuning techniques utilize predictive algorithms designed to predict the likely performance of a cache based upon a hypothetical cache size setting. Similarly, some have tuned a cache to a particular size in order to achieve a desired cache hit rate without knowing a priori whether the selected cache size can achieve the desired hit rate. Analogously, cache tuning methodologies have computed a proper eviction strategy for cached objects based upon a proposed albeit unimplemented size of a cache. In all circumstances, though, the process of reaching an optimal cache size can be slow and inefficient.